Embodiments of the inventive concept relate to non-volatile memory devices, and more particularly, to non-volatile multi-level (NVML) memory devices capable of reducing read errors caused by coupling effects between proximate memory cells in a constituent memory cell array. Embodiments of the inventive concept also relate to read methods used to read the state of NVML memory cells in such NVML memory devices.
Multi-level memory cells are respectively capable of storing two or more bits in a single memory cell. This ability enables significant improvements in the data storage density per unit area of memory cell arrays. With the demand on high-capacity NAND flash memory products, the number of bits capable of being stored in a NVML memory cell (hereinafter, referred to as a “cell”) has increased. Information in the form of digital data values is stored in each cell according to different threshold voltages states. Thus, programming operations are used to define a particular state to “write” a data value to the cell, while read operations are used to determine the state of the cell to “read” the data value of the cell. As the number of bits stored in a cell increases, the degree of cell integration also increases and various types of interference occur. Coupling effects between adjacent (or proximate) cells in a memory cell array are one type of interference.
Inter-cell coupling usually includes bit-line coupling along a column direction and word-line coupling in a row direction. Inter-cell coupling of any type can cause read errors. Erased cells (memory cells intended to be in the erase state) are relatively more affected by the word-line coupling than programmed cells (memory cells intended to be in one of a plurality of programmed states). Accordingly, a read error is more likely to occur during a read operation using a read voltage to distinguish (or discriminate) between an erased cell and a programmed cell.